The present invention relates generally to CMOS integrated circuit devices and processes, and more particularly, to an improved radiation hard, high voltage analog CMOS device fabrication process.
Some military applications require integrated circuit devices that have a relatively high operating voltage and that operate in a radiation environment. For example, focal plane array devices require high voltage clock bias circuits operating at voltages of at least 15 V. In addition, some focal plane array devices must operate in a radiation environment. Presently available integrated circuit devices fabricated with conventional radiation hard CMOS processes are typically limited to operation at a voltage of 10 V or less, due to relatively low N.sup.+ to P-well junction breakdown voltages.
The conventional procedure for fabricating these devices typically involves providing a silicon substrate having a first conductivity type, and forming first well regions having a second conductivity type in the substrate. This is achieved by masking and depositing dopant ions into the surface of the substrate, epitaxially growing silicon on top of the doped substrate and then heating the substrate to form a buried layer that defines second conductivity type wells. Second well regions are defined adjacent to the first well regions. Channel stops are then formed surrounding the P-and N-channel regions. A field oxide layer is deposited on the substrate, and it is masked and etched to define active areas. A gate oxide layer is grown on the substrate above the active areas, and polysilicon gates are formed thereon. Finally, dopant ions are implanted through the field oxide layer and into source and drain regions using the polysilicon gates and field oxide layer as a mask. The devices fabricated using this process have N.sup.+ (source and drain regions) to P-well junction breakdown voltages in the 10-12 volt range.
Accordingly, it would be an advance in the integrated circuit processing art to have an improved analog CMOS process that provides for radiation hard, high voltage integrated circuit devices having junction breakdown voltages above 12 volts. It is therefore an objective of the present invention to provide a fabrication process for integrated circuit devices that operate at relatively high voltages. Another objective of the present invention is to provide a process of fabricating integrated circuit devices that are radiation hard.